This is the circuit I'm going to build,
From a main oscillator of frequency (f_m), a frequency divider (IC1A) supplies values of f_m/2, f_m/8, and f_m/16. Acceptable values of f_m depend on the selected CMOS technology. The circuit has been tested at f_m = 2 MHz with basic CMOS logic, and at 20 MHz with HCMOS.

Dibits are formed from a digital input (PCM signal) in shift register IC2B, and in the dual flip-flop IC3. The different phases of 0º, 90º, 180º, and 270º are produced at outputs QA, QB, QC, and QD of the four-bit shift register, IC2A.

Finally, the dibits (on pins A and B of IC4) control the multiplexer (data selector) output. This is a selected phase from D0, D1, D2, or D3, according to the dibit combinations. The rest of the circuit is a simple band-pass filter that eliminates dc levels and shapes the pulse, plus an amplifier to set the desired output level. The QPSK output frequency is f_m/8.